The encoding and decoding of cyclic codes having a parity bit based on a parity polynomial is described in "Error Control Coding" by Lin et al. published by Prentice-Hall Publishing, 1983. As discussed in Lin et al., encoding cyclic codes generally begins by multiplying a signal polynomial by a specified coefficient. The result of this multiplication is then divided by a check polynomial and the remainder obtained. Finally, the remainder obtained from the check polynomial division is added to the result of the multiplication of the signal polynomial and the coefficient. This procedure of encoding a cyclic code is based on processing bit-serial input data. Accordingly, multiple clock cycles are required for the operation.
In a similar manner, error detection of cyclically coded data may be carried out as described in Lin et al. by determination of a syndrome which is "0" only if there are no errors in the received code vector. This operation also can be carried out as a bit-wise serial operation as seen in FIG. 4.5 on page 99 of Lin et al. but would, likewise, generally require multiple clock cycles for the operation.
In summary, as a result of the bit-wise serial operation of error detection, the detection of errors generally requires multiple clock cycles which may cause an increase in the power consumption of the device. Furthermore, the detection of errors may be delayed by the number of clock cycles it takes to serially process the data. Accordingly, there is a need for improvement in the error detection of cyclically coded information.